This patent relates to a method for fabricating a semiconductor device, and more particularly, to a method for verifying a pattern of a semiconductor device.
With the increase in integration degree of semiconductor devices, patterns required in semiconductor devices shrink in size gradually, which leads to pattern defects, e.g., a pattern bridge or a pinch fail, on an actual wafer due to limitations in a manufacturing process of semiconductor devices. Accordingly, before the verification of designed target patterns and the preparation of a mask, weak or defective parts in view of processes are detected in advance and the detection results are then reflected in a design layout.
One of a conventional method for verifying pattern defects has been suggested, where an image of patterns formed on an actual wafer is compared with an original layout and then different parts there between resulted from the comparison are detected as defects. However, the original layout may be modified several times so as to be favorable to wafer patterning while an actual wafer process is performed. Once the original layout is modified, different parts between patterns on the actual wafer and a modified layout are detected as defects in the verification of pattern defects. Parts modified from the original layout are detected as the defects. Therefore, it is difficult to detect defects occurring on the actual wafer, e.g., pattern bridges or pinch fails.